IBM Research Alliance Details New Nanosheet Transistors for 5nm Chips

By Charles King, Pund-IT, Inc.  June 7, 2017

IBM and its Research Alliance partners, including GLOBALFOUNDRIES and Samsung announced that they have developed an industry-first process for building silicon nanosheet transistors that will enable 5 nanometer (nm) chips. Microprocessors manufactured with this process will incorporate as many as 30B switches on a fingernail sized chip, half again as many as the 7nm/20B transistor chips the Alliance announced less than two years ago.

Scientists at the SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering’s NanoTech Complex in Albany, NY who work with the alliance used stacks of silicon nanosheets as the transistor device structure. This breakthrough design can replace the standard FinFET architecture the semiconductor industry has used up through existing 7nm node technologies.

The Alliance-led effort is the first to demonstrate the feasibility of designing and fabricating stacked nanosheet devices that support electrical properties superior to FinFET. It also successfully extends the exploratory work in nanosheet semiconductor technologies that IBM has pursued for over a decade.

According to IBM, compared to existing leading-edge 10nm chips, nanosheet-based 5nm technologies can deliver as much as 40 percent performance enhancements at fixed power, or 75 percent power savings at matched performance.

Those improvements should help accelerate cognitive computing, the Internet of Things (IoT), and other data-intensive applications delivered in the cloud. The resulting power savings could also result in smart phone and mobile device batteries lasting two to three times longer between charges than today’s products.

In sum, IBM and its Research Alliance partners have proven that 5nm chips are possible, that they are potentially more powerful than current FinFET solutions and that the availability of 5nm chips is not too far off in the future.

Final analysis

The technology industry is rightly respected, even revered for the innovative computing products that regularly appear in the market. But underlying those solutions are equally, often even more innovative manufacturing processes. That highlights a practical truth about IT: you can have all the bright ideas in the world but unless you can successfully build and reliably produce commercial products, bright ideas stay locked in a desk drawer.

What does that have to do with the announcement by IBM and its Research Alliance partners? That more barriers to producing ever smaller, increasingly powerful and more energy efficient computer chips have fallen.

To be clear, this is not the first time that 5nm transistors have been created. IBM itself produced a 6nm transistor in 2002 and NEC demonstrated a 5nm transistor the following year. Following that, various technology vendors and research labs created unique, smaller transistors and working gates.

But in the words of Dr. Bernie Meyerson, IBM’s Chief Innovation Officer, when you reach atomic (5nm or less) levels, “life gets complicated.” In semiconductor terms, that translates into increasing limitations on materials’ current-carrying capabilities and other problematic issues.

What does that mean in practical terms? Creating a 5nm transistor is difficult in the extreme but assembling billions of the little suckers into a working microprocessor is exponentially harder. And creating processes to reliably manufacture those chips exponentially harder than that.

And that’s exactly what IBM and its Research Alliance partners have done.

Why is it so hard? First, consider what 5nm means in terms of size. There are 25,400,000 nanometers in an inch, a sheet of paper is 100,000nm thick and a human hair is about 80,000nm to 100,000nm wide. A single strand of human DNA is about 2.5nm in diameter or half the thickness of the new 5nm chips.

You get the nearly invisible, almost unimaginable picture.

The Research Alliance scientists and team use of silicon nanosheets is also a first, and represents a significant departure from alternative future-looking designs utilizing nanowire. In both cases (as well as in traditional FinFET designs) an elemental goal is to increase the total number of transistors on the chip while maintaining or shrinking its footprint.

Most Nanowire-based solutions follow FinFET designs by stacking nanowires into tall, thin, tightly pitched fins. But Alliance researchers found that approach tends to perform poorly and suffer other imitations. In contrast, using silicon nanosheets resulted in stacked fins which, though thicker than nanowire designs, achieved optimal power/performance gains while minimizing other problems.

By applying the same Extreme Ultraviolet (EUV) lithography approach used in its 7nm test node, the Alliance team was also able to continuously adjust the width of the nanosheets, thus permitting specific circuits to be fine-tuned for increased performance and power. As IBM noted, FinFET chips can scale to 5nm but reducing the space between the fins does not support increased current flow for additional performance.

So what comes next? More work of course. IBM and its Research Alliance partners now have to make 5nm processors cost-effectively replicable and their manufacturing processes commercially scalable.

What does that mean in terms of the market? Not much in the short term. Next gen 10nm chips from Intel and Qualcomm are nearing production and pilot production of future generation 7nm chips isn’t far away. At the same time, other vendors will continue pressing their own 5nm development efforts.

While worthy of respect, those competitive concerns shouldn’t detract from what IBM, GLOBALFOUNDRIES, Samsung and the other Global Alliance members have achieved. By proving that what was once considered impossible is possible, IBM and its partners are showing a clear way forward to new computing capabilities and innovations.

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